t/t7407: fix two typos in submodule tests

diff --git a/t/t2030-unresolve-info.sh b/t/t2030-unresolve-info.sh
index 0b699f50dd17b884c391135c2e18ca6b6df0b51a..309199bca272b63499ca69edbb953bcc8c770ecc 100755 (executable)
--- a/t/t2030-unresolve-info.sh
+++ b/t/t2030-unresolve-info.sh
@@ -54,8 +54,11 @@ test_expect_success setup '
        test_commit second fi/le second &&
        git checkout side &&
        test_commit third fi/le third &&
+       git branch add-add &&
        git checkout another &&
        test_commit fourth fi/le fourth &&
+       git checkout add-add &&
+       test_commit fifth add-differently &&
        git checkout master
 '
 
@@ -179,4 +182,14 @@ test_expect_success 'rerere forget (binary)' '
        git rerere forget binary
 '
 
+test_expect_success 'rerere forget (add-add conflict)' '
+       git checkout -f master &&
+       echo master >add-differently &&
+       git add add-differently &&
+       git commit -m "add differently" &&
+       test_must_fail git merge fifth &&
+       git rerere forget add-differently 2>actual &&
+       test_i18ngrep "no remembered" actual
+'
+
 test_done