t / t4110 / expecton commit diff: cache textconv output (d9bae1a)
   1a1
   2a11
   3a111
   4a1111
   5b1
   6b11
   7b111
   8b1111
   9b2
  10b22
  11b222
  12b2222
  13c1
  14c11
  15c111
  16c1111
  17c2
  18c22
  19c222
  20c2222